1. Field of the Invention
The present invention relates to a semiconductor integrated circuit configured of a dynamic random access memory (usually referred to as the DRAM) including semiconductor devices such as a plurality of MOS field-effect transistors (hereinafter referred to as MOS transistors or MOS FETs).
In recent years, a DRAM intended to improve the density, in which a plurality of memory cells of one-transistor/one-capacitor type each having a single nMOS transistor and a single capacitor are formed on a chip, has become available. In the case of using nMOS transistors (an abbreviation for n-channel MOS field-effect transistors) as cell transistors for writing data to the memory cells or as bit line transfer transistors for reading out data from the memory cells by a sense amplifier of shared type in order to realize a high integration of a semiconductor integrated circuit including a DRAM or the like, it is necessary to consider an influence of a threshold voltage between a gate and a source of each nMOS transistor.
In order to eliminate the influence of the threshold voltage of the nMOS transistors and stabilize the operation of writing to and reading from a plurality of the memory cells in the DRAM, a step-up voltage is generated which is higher, by at least the above-mentioned threshold level, than a source of each nMOS transistor used as a cell transistor or as a bit line transfer transistor (i.e. a step-up voltage is generated which is higher, by at least the threshold voltage, than a high voltage level of each bit line), and this step-up voltage is supplied to the gate voltage of the nMOS transistor.
The present invention refers to a method of preventing an excessive rise of the voltage level at a step-up node for producing a step-up voltage at the time of a burn-in test conducted on the semiconductor integrated circuit using such a step-up voltage.
2. Description of the Related Art
First, in order to facilitate the understanding the problems encountered when generating a step-up voltage to stabilize write and read operations for a plurality of memory cells in the DRAM constituting a semiconductor integrated circuit, the configuration and operation of a gate voltage generating portion of a cell transistor and a gate voltage generating portion of a bit line transfer transistor will be explained with reference to the accompanying drawings (FIGS. 1 to 3).
FIG. 1 is a circuit block diagram showing a configuration of a cell transistor used in an ordinary DRAM; FIG. 2 is a circuit block diagram showing a configuration a bit line transfer transistor of the DRAM; and FIG. 3 is a diagram showing an operation voltage waveform at the time of reading cell data in the DRAM. In this specification, for distinction from the peripheral circuit in the semiconductor integrated circuit, the gate voltage generating portion of the cell transistor and the gate voltage generating portion of the bit line transfer transistor in the memory block including a plurality of memories are collectively called a core circuit portion.
As shown in FIG. 1, each of the memory cells of the one-transistor/one-capacitor type currently used includes a cell transistor Tc having a nMOS transistor, and a cell capacitor Cc. In the case in which data "1" or data "0" is written in this type of memory cell through a bit line BL, it is necessary to activate (turn on) a cell transistor Tc by applying an output voltage of high voltage level to the cell transistor Tc from a word decoder 70 connected to a word line WL. Further, in order to increase the voltage change generated by stored charge Qs in the cell capacitor Cc and thus to read the data into the memory cell without any error, the gate is required is to be supplied with an input voltage sufficiently high to guarantee a stable operation of the cell transistor Tc.
In such a case, however, as shown in the operation voltage waveform diagram of FIG. 3, the voltage change across the stored charge Qs is reduced by an amount equivalent to the gate-source threshold voltage Vth of the transistor Tc. In order to obviate the effect of the threshold voltage Vth, a step-up source voltage SVii (see FIG. 1) generated by an internal step-up voltage generating unit is used to supply the word line WL with a step-up voltage higher than the source or the drain of the nMOS transistor by the above-mentioned threshold voltage or more. On the other hand, as shown in FIG. 2, assume that data is read by a shared-type senser amplifier 72 (using a reference voltage Vii) from one of two pairs of bit lines including BLX(n), BLZ(n) and BLX(n+1), BLZ(n+1). It is necessary to activate (turn on) the corresponding one of the pairs of read transistors Tx(n), Tz(n) and read transistors Tx(n+1), Tz(n+1) by a bit line transfer signal BLTX(n) or BLTX(n+1) of a step-up voltage level output from bit line transfer signal generating units 71-1, 71-2, respectively. Further, it is necessary to supply the bit line transfer signal BLTX having a voltage level sufficiently high to assure stable operation of the sense amplifier 72.
In such a case, however, in order to obviate the influence of the threshold voltage Vth and assure the read operation of data without error, the step-up voltage source SVii (see FIG. 2) is used for the bit line transfer signal generating units 71-1, 71-2 to supply a bit line transfer signal BLTX having a step-up voltage output level higher by the threshold voltage value than the source or the drain of the nMOS transistor.
FIG. 4 is a circuit diagram showing a circuit configuration for precharging a step-up node for burn-in entry according to the prior art.
Conventionally, a precharge portion is provided for precharging the step-up node for outputting a step-up voltage before carrying out a burn-in test for a semiconductor integrated circuit, as shown in FIG. 4, in order to assure normal operation of the internal step-up voltage generating unit at the time of burn-in test. The step-up voltage generating unit having the precharge portion (141 to 145, 241 to 244) for precharging the step-up node is usually called a step-up voltage pumping circuit portion.
More specifically, in the conventional step-up voltage pumping circuit portion, a step-up voltage pumping control signal is generated by a plurality of inverters 150 and a level shifter 155. This signal is supplied to a pair of pMOS transistors 133 through a pair of precharge diodes 131, 132 (diodes provided separately from the diodes 141, 241 in the precharge portion) and inverters 130, 134. In the process, a step-up voltage is generated by capacitors 135, 136 based on the control signal. The drains of the pMOS transistors 133 form a step-up node for producing a step-up voltage (SVcc) generated by the capacitors 135, 136. The precharge portion for precharging the step-up node includes a pair of precharge nMOS transistors 144, 244, a nMOS transistor 143 connected to the gate of one of the precharge transistors, and a nMOS transistor 243 connected to the gate of the other precharge transistor.
Further, the input terminal of the precharge nMOS transistor 144 of the precharge portion is connected with a capacitor 140 and the diodes 141, 142. The input terminal of the other precharge nMOS transistor 244 of the precharge portion, on the other hand, is connected with a capacitor 240 and the diodes 241, 242. The gates of the precharge nMOS transistors 144, 244 are supplied with precharge signals of opposite polarities by an inverter 145.
In the conventional internal step-up voltage generating unit shown in FIG. 4, in order to prevent the voltage level in the step-up node from excessively increasing at the time of burn-in when the burn-in test is conducted, the gates of the precharge nMOS transistors 144, 244 are floated using a burn-in entry signal bih indicating that a burn-in test is being conducted and the pumping of the gate voltage is prohibited (1 of FIG. 4). Further, the level of the precharge voltage of the step-up node connected to the sources of the precharge nMOS transistors 144, 244 is set lower than the normal operation range (2 of FIG. 4) (for example, to the neighborhood of the drain voltage Vcc less the threshold voltage Vth.
FIG. 5 is a circuit diagram showing a configuration of the essential circuit parts for explaining a first problem point of the prior art; FIG. 6 is a graph showing the manner in which the precharge voltage level undergoes a change in FIG. 5; and FIG. 7 is a graph showing the manner in which the voltage across the step-up node increases in FIG. 5.
The circuit of FIG. 5 is enlarged from the configuration of the precharge portion shown in FIG. 4. In the case where a nMOS transistor is used for precharging the step-up node in the step-up voltage pumping circuit portion of the type shown in FIG. 5, the gate voltage (at node n01) of the nMOS transistor is floated between Vcc-Vth and Vcc+Vth. Assume, for example, that the the gate voltage of the node n01 providing a floating node is Vcc+Vth. As shown in the graph of FIG. 6, the precharge voltage level applied to the step-up node n02 is undesirably increased beyond Vcc.
As a result, as shown in FIG. 7, the voltage at a connecting point pmpz (at a connecting point pmplz in FIG. 4, for example) across the capacitor Cn02 (a capacitor 135 in FIG. 4, for example) and the voltage across the node n02 increase to such an extent as to exceed the breakdown voltage of the transistors (a pair of nMOS transistors 133 shown in FIG. 4, for example) for producing a step-up voltage, thus posing a problem in that the transistors are destroyed.
FIG. 8 is a circuit diagram showing a configuration of the essential circuit parts for explaining a second problem point of the prior art. FIG. 9 is a graph showing the manner in which the charge escapes from the step-up node to the drain in FIG. 8.
As shown in FIG. 8, the gate voltage of the node n01 constituting a floating node can assume a value between Vcc-Vth and Vcc+Vth, and therefore the precharge nMOS transistor 144 (or 244) turns on. As a result, a current path is created between the step-up voltage SVcc and the drain voltage Vcc and a current I flows with the result that charge escapes from the node n02 toward the drain.
Consequently, as shown in FIG. 9, even after a burn-in test is started, the charge effectively contributing to the precharge operation partially escapes, thereby giving rise to the problem that the voltage across the node n02 fails to rise smoothly and the step-up efficiency is considerably deteriorated.